Data storage devices (DSDs), such as disk drives and solid state drives, are employed in numerous applications such as computer systems (e.g., desktops, laptops, portables, servers, etc.) and consumer devices (e.g., music players, cell phones, cameras, etc.). Business solutions (enterprise computing) typically employ higher end DSDs, such as Serial Attached SCSI (SAS), that support features such as fiber channel for implementing multiple initiators and full duplex communication. In order to achieve the higher throughput demanded by enterprise computing, high end DSDs typically employ multiple processors performing tasks in parallel. FIG. 1 shows an example high end prior art DSD comprising a host interface state machine 2 and a host interface processor 4 for implementing host interface functions, and a master processor 6 for executing access commands (read/write) using dedicated interface circuitry 8 that interfaces with a non-volatile memory 10 (e.g., a disk or semiconductor memory). A data buffer 12 buffers write data during write operations and read data during read operations.
The host interface state machine 2 implements a suitable protocol to communicate with the host and receive access commands (read/write). When an access command is received, the host interface processor 4 is notified so that it may generate control structures for the host interface state machine 2 needed to process the access command. The host interface processor 4 also transmits command information to the master processor 6 which executes the access command by accessing the NVM 10 through the NVM interface 8. Conventionally, the master processor 6 signals the host interface processor 4 that a write command has completed when the write data has been written to the NVM 10, and that a read command has completed (or partially completed) when read data is in the data buffer 12 and ready for transmission to the host. The delay that results from this inter-processor communication decreases throughput of the DSD since it delays the host interface state machine 2 executing the control structures needed to communicate with the host.